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LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 LM20333 36v, 3a synchronous buck regulator with frequency synchronization check for samples: LM20333 1 features description the LM20333 is a full featured synchronous buck 2 ? 4.5v to 36v input voltage range regulator capable of delivering up to 3a of load ? 3a output current, 5.2a peak current current. the current mode control loop is externally ? 130 m ? /110 m ? integrated power mosfets compensated with only two components, offering both high performance and ease of use. the device is ? 94% peak efficiency with synchronous optimized to work over the input voltage range of rectification 4.5v to 36v making it well suited for high voltage ? 1.5% feedback voltage accuracy systems. ? current mode control, selectable the device features internal over voltage protection compensation (ovp) and over current protection (ocp) circuits for ? oscillator synchronization from 250khz to increased system reliability. a precision enable pin 1.5mhz and integrated uvlo allows the turn on of the device to be tightly controlled and sequenced. startup inrush ? adjustable output voltage down to 0.8v currents are limited by both an internally fixed and ? compatible with pre-biased loads externally adjustable soft-start circuit. fault detection ? programmable soft-start with external and supply sequencing are possible with the capacitor integrated power good (pgood) circuit. ? precision enable pin with hysteresis the LM20333 is designed to work well in multi-rail ? ovp, uvlo inputs and pgood output power supply architectures. the output voltage of the device can be configured to track a higher voltage rail ? internally protected with peak current limit, using the ss/trk pin. if the output of the LM20333 is thermal shutdown and restart pre-biased at startup it will not sink current to pull the ? accurate current limit minimizes inductor output low until the internal soft-start ramp exceeds size the voltage at the feedback pin. ? non-linear current mode slope compensation the switching frequency of the LM20333 can be ? 20-pin htssop exposed pad package synchronized to an external clock by use of the sync pin. the sync pin is capable of synchronizing applications to input signals ranging from 250 khz to 1.5 mhz. ? simple to design, high efficiency point of the LM20333 is offered in an exposed pad 20-pin load regulation from a 4.5v to 36v bus htssop package that can be soldered to the pcb, eliminating the need for bulky heatsinks. ? high performance dsps, fpgas, asics and microprocessors ? communications infrastructure, automotive 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008 ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com simplified application circuit connection diagram figure 1. 20-pin htssop, top view see pwp0020a package pin descriptions pin(s) name description application information 1 ss/trk soft-start or tracking control input an internal 4.5 a current source charges an external capacitor to set the soft-start rate. the pwm can track to an external voltage ramp with a low impedance source. if left open, an internal 1 ms ss ramp is activated. 2 fb feedback input to the error amplifier this pin is connected to the inverting input of the internal from the regulated output transconductance error amplifier. an 800 mv reference is internally connected to the non-inverting input of the error amplifier. 3 pgood power good output signal open drain output indicating the output voltage is regulating within tolerance. a pull-up resistor of 10 k ? to 100 k ? is recommended if this function is used. 4 comp output of the internal error amplifier and the loop compensation network should be connected between the input to the pulse width modulator comp pin and the agnd pin. 5,6,15,16 vin input supply voltage nominal operating range: 4.5v to 36v. 7,8,13,14 sw switch pin the drain terminal of the internal synchronous rectifier power nmosfet and the source terminal of the internal control power nmosfet. 9,10,11 gnd ground internal reference for the power mosfets. 12 agnd analog ground internal reference for the regulator control functions. 17 boot boost input for bootstrap capacitor an internal diode from vcc to boot charges an external capacitor required from sw to boot to power the control mosfet gate driver. 18 vcc output of the high voltage linear vcc tracks vin up to about 7.2v. above vin = 7.2v, vcc is regulated regulator. the vcc voltage is regulated to approximately 5.5 volts. a 0.1 f to 1 f ceramic decoupling to approximately 5.5v. capacitor is required. the vcc pin is an output only. 2 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333 vin 1 fb ss/trk sw vin gnd agnd sw en vin pgood comp ep vcc 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sw gnd gnd sw vin sync boot c in vin sw agnd fb pgood v out r fb1 r fb2 c out en ss/trk vcc c vcc c c1 comp r c1 v in LM20333 boot gnd l c boot d1 (optional) sync
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 pin descriptions (continued) pin(s) name description application information 19 en enable or uvlo input an external voltage divider can be used to set the line undervoltage lockout threshold. if the en pin is left unconnected, a 2 a pull-up current source pulls the en pin high to enable the regulator. 20 sync frequency synchronization input an external clock connected to this pin will set the switching frequency. if left open the device will operate at approximately 200 khz. ep exposed exposed pad exposed metal pad on the underside of the package with a weak pad electrical connection to gnd. connect this pad to the pc board ground plane in order to improve heat dissipation. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 3 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com absolute maximum ratings (1) (2) vin to gnd -0.3v to +38v boot to gnd -0.3v to +43v boot to sw -0.3v to +7v sw to gnd -0.5v to +38v sw to gnd (transient) -1.5v ( < 20 ns) fb, en, ss/trk, comp, sync, pgood to gnd -0.3v to +6v vcc to gnd -0.3v to +8v storage temperature -65 c to 150 c esd rating human body model (3) 2kv (1) absolute maximum ratings indicate limits beyond witch damage to the device may occur. operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. for ensured specifications and test conditions, see the electrical characteristics. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. (3) the human body model is a 100 pf capacitor discharged through a 1.5 k ? resistor to each pin. operating ratings vin to gnd +4.5v to +36v junction temperature ? 40 c to + 125 c electrical characteristics unless otherwise stated, the following conditions apply: v vin = 12v. limits in standard type are for t j = 25 c only, limits in bold face type apply over the junction temperature (t j ) range of -40 c to +125 c. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. symbol parameter conditions min typ max units v fb feedback pin voltage v vin = 4.5v to 36v 0.788 0.8 0.812 v r hsw-ds(on) high-side mosfet on-resistance i sw = 3a 130 225 m ? r lsw-ds(on) low-side mosfet on-resistance i sw = 3a 110 190 m ? i q operating quiescent current v vin = 4.5v to 36v 2.3 3 ma i sd shutdown quiescent current v en = 0v 150 180 a v uvlo vin under voltage lockout rising v vin 4 4.25 4.5 v v uvlo(hys) vin under voltage lockout hysteresis 350 450 mv v vcc vcc voltage i vcc = -5 ma, v en = 5v 5.5 v i ss soft-start pin source current v ss = 0v 2 4.5 7 a v trkacc soft-start/track pin accuracy v ss = 0.4v -10 5 15 mv i boot boot diode leakage v boot = 4v 10 na v f-boot boot diode forward voltage i boot = -100 ma 0.9 1.1 v powergood v fb(ovp) over voltage protection rising threshold v fb(ovp) / v fb 107 110 112 % v fb(ovp-hys) over voltage protection hysteresis vfb(ovp) / v fb 2 3 % v fb(pg) pgood threshold, v out rising v fb(pg) / v fb 93 95 97 % v fb(pg-hys) pgood hysteresis v fb(pg) / v fb 2 3 % t pgood pgood delay 20 s i pgood(snk) pgood low sink current v pgood = 0.5v 0.6 1 ma i pgood(src) pgood high leakage current v pgood = 5v 5 200 na oscillator f osc oscillator frequency v sync = 0v 160 200 240 khz f osch maximum sync frequency 1500 khz 4 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 electrical characteristics (continued) unless otherwise stated, the following conditions apply: v vin = 12v. limits in standard type are for t j = 25 c only, limits in bold face type apply over the junction temperature (t j ) range of -40 c to +125 c. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. symbol parameter conditions min typ max units f oscl minimum sync frequency 250 khz v ih_sync sync pin logic high 2 v v il_sync sync pin logic low 0.8 v i sync sync pin input leakage v sync = 5v 10 na t min minimum off time i load = 3a 170 ns error amplifier i fb feedback pin bias current v fb = 1v 50 na i comp(src) comp output source current v fb = 0v 200 400 a v comp = 0v i comp(snk) comp output sink current v fb = 1.6v 200 350 a v comp = 1.6v g m error amplifier dc transconductance i comp = -50 a to +50 a 450 515 600 mho a vol error amplifier voltage gain comp pin open 2000 v/v gbw error amplifier gain-bandwidth product comp pin open 7 mhz current limit i lim cycle by cycle positive current limit 4.3 5.2 6.0 a i limneg cycle by cycle negative current limit 2.8 a t ilim cycle by cycle current limit delay 150 ns enable v en(rising) en pin rising threshold 1.2 1.25 1.3 v v en(hys) en pin hysteresis 50 mv i en en source current v en = 0v, v vin = 12v 2 a thermal shutdown t sd thermal shutdown 170 c t sd(hys) thermal shutdown hysteresis 20 c thermal resistance jc junction to case 5.6 c/w ja junction to ambient (1) 0 lfm airflow 27 c/w (1) measured on a 4 layer 2 " x 2 " pcb with 1 oz. copper weight inner layers and 2 oz. outer layers. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 5 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com typical performance characteristics unless otherwise specified: v vin = 12v, v out = 3.3v, l= 4.7 h, f sw =750khz, c ss = 100nf, t a = 25 c for efficiency curves, loop gain plots and waveforms, and t j = 25 c for all others. efficiency efficiency vs. vs. load current load current f sw = 350 khz f sw = 500 khz figure 2. figure 3. efficiency vs. load current f sw = 750 khz error amplifier gain figure 4. figure 5. error amplifier phase line regulation figure 6. figure 7. 6 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 typical performance characteristics (continued) unless otherwise specified: v vin = 12v, v out = 3.3v, l= 4.7 h, f sw =750khz, c ss = 100nf, t a = 25 c for efficiency curves, loop gain plots and waveforms, and t j = 25 c for all others. v cc vs. load regulation v in figure 8. figure 9. non-switching i q shutdown i q vs. vs. v in v in figure 10. figure 11. pgood output low level voltage enable threshold and hysteresis vs. vs. i pgood temperature figure 12. figure 13. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 7 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com typical performance characteristics (continued) unless otherwise specified: v vin = 12v, v out = 3.3v, l= 4.7 h, f sw =750khz, c ss = 100nf, t a = 25 c for efficiency curves, loop gain plots and waveforms, and t j = 25 c for all others. uvlo threshold and hysteresis enable current vs. vs. temperature temperature figure 14. figure 15. high-side fet resistance vs. clock synchronization temperature figure 16. figure 17. low-side fet resistance vs. temperature load transient response figure 18. figure 19. 8 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 typical performance characteristics (continued) unless otherwise specified: v vin = 12v, v out = 3.3v, l= 4.7 h, f sw =750khz, c ss = 100nf, t a = 25 c for efficiency curves, loop gain plots and waveforms, and t j = 25 c for all others. peak current limit vs. temperature startup with prebiased output figure 20. figure 21. startup with c ss = 0 startup with c ss = 100 nf figure 22. figure 23. startup with applied track signal figure 24. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 9 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com block diagram 10 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333 5.2a + - fb comp control logic en current limit overvoltage undervoltage error amp pwm comparator ss/trk pgood + - +5.5v regulator vcc boot vcc thermal protection gnd sw vin current sense vcc 1.25v boot boot uvlo 4.25v agnd + 740 mv 880 mv pg-l pg-l 2.7v g m = 515 p mho vref + - 800 mv + - + 2 p a discharge discharge slope comp 4.5 p a + - -2.8a negative current limit +2.7v regulator 2.7v + - + - + - + - phase lock loop sync internal +5.5v regulator vcc_int vcc_int enable_int enable_int
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 operation description general the LM20333 switching regulator features all of the functions necessary to implement an efficient buck regulator using a minimum number of external components. this easy to use regulator features two integrated switches and is capable of supplying up to 3a of continuous output current. the regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient response over the entire output voltage range. peak current mode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. the switching frequency can be synchronized to an external oscillator over the range of 250 khz to 1.5 mhz. the sync function allows the device to operate at high switching frequencies minimizing the size of the inductor while still achieving efficiencies as high as 94%. the precision internal voltage reference allows the output to be set as low as 0.8v. fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. the device is available in the htssop package featuring an exposed pad to aid thermal dissipation. the typical application circuit for the LM20333 is shown in figure 25 in the design guide. precision enable the enable (en) pin allows the output of the device to be enabled or disabled with an external control signal. this pin is a precision analog input that enables the device when the voltage exceeds 1.25v (typical). the en pin has 50 mv of hysteresis and will disable the output when the enable voltage falls below 1.2v (typical). if the en pin is not used, it should be disconnected so the internal 2 a pull-up will default this function to the enabled condition. since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from v in to configure the device to turn-on at a precise input voltage. the precision enable circuitry will remain active even when the device is disabled. frequency synchronization the frequency sychronization pin(sync) allows the switching frequency of the device to be controlled with an external clock signal. this feature allows the user to sychronize multiple converters, avoiding undesirable frequency bands of operation. the switching frequency of the device will synchronize to the rising edge of the clock source that is driving the sync pin. the logic low level for the input clock must be below 0.8v and the logic high level must exceed 2.0v to ensure proper operation. the device will synchronize to frequencies from 250 khz to 1.5 mhz. if the synchronization clock is removed or not present during startup, the oscillator of the device will run at approximately 200 khz. if the sync pin is not used it should be connected to ground. peak current mode control in most cases, the peak current mode control architecture used in the LM20333 only requires two external components to achieve a stable design. the compensation can be selected to accommodate any capacitor type or value. the external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device. for duty cycles above 50% all peak current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. this artificial linear ramp is commonly referred to as slope compensation. what makes the LM20333 unique is the amount of slope compensation will change depending on the output voltage. when operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. this is accomplished in the LM20333 by using a non-linear parabolic ramp for the slope compensation. the parabolic slope compensation of the LM20333 is an improvement over the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 11 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com current limit the precise current limit enables the device to operate with smaller inductors that have lower saturation currents. when the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side fet turns off and the low-side fet turns on, allowing the inductor current to ramp down until the next switching cycle. for each sequential over-current event, the reference voltage is decremented and pwm pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. soft-start and voltage tracking the ss/trk pin is a dual function pin that can be used to set the startup time or track an external voltage source. the startup or soft-start time can be adjusted by connecting a capacitor from the ss/trk pin to ground. the soft-start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling startup current. if no soft-start capacitor is used the device defaults to the internal soft-start circuitry resulting in a startup time of approximately 1 ms. for applications that require a monotonic startup or utilize the pgood pin, an external soft-start capacitor is recommended. the ss/trk pin can also be set to track an external voltage source. the tracking behavior can be adjusted by two external resistors connected to the ss/trk pin as shown in figure 30 in the design guide. pre-bias startup capability the LM20333 is in a pre-biased state when it starts up with an output voltage greater than zero. this often occurs in many multi-rail applications such as when powering an fpga, asic, or dsp. in these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. even though the LM20333 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. during start up the LM20333 will not sink current until the soft-start voltage exceeds the voltage on the fb pin. since the device cannot sink current, it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. power good and over voltage fault handling the LM20333 has built in under and over voltage comparators that control the power switches. whenever there is an excursion in output voltage above the set ovp threshold, the part will terminate the present on-pulse, turn- on the low-side fet, and pull the pgood pin low. the low-side fet will remain on until either the fb voltage falls back into regulation or the negative current limit is triggered which in turn tri-states the fets. if the output reaches the uvp threshold the part will continue switching and the pgood pin will be deasserted and go low. typical values for the pgood resistor are on the order of 100 k ? or less. to avoid false tripping during transient glitches the pgood pin has 20 s of built in deglitch time to both rising and falling edges. uvlo the LM20333 has an internal under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 4.25v (typical). the uvlo threshold has 350 mv of hysteresis that keeps the device from responding to power-on glitches during start up. if desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to v in as shown in figure 29 in the design guide. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated, typically at 170 c, the LM20333 tri-states the power fets and resets soft-start. after the junction cools to approximately 150 c, the part starts up using the normal start up routine. this feature is provided to prevent catastrophic failures from accidental device overheating. 12 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 design guide this section walks the designer through the steps necessary to select the external components to build a fully functional power supply. as with any dc-dc converter numerous trade-offs are possible to optimize the design for efficiency, size, or performance. these will be taken into account and highlighted throughout this discussion. to facilitate component selection discussions the circuit shown in figure 25 below may be used as a reference. unless otherwise indicated all formulas assume units of amps (a) for current, farads (f) for capacitance, henries (h) for inductance and volts (v) for voltages. figure 25. typical application circuit the first equation to calculate for any buck converter is duty-cycle. ignoring conduction losses associated with the fets and parasitic resistances it can be approximated by: (1) inductor selection (l) the inductor value is determined based on the operating frequency, load current, ripple current and duty cycle. the inductor selected should have a saturation current rating greater than the peak current limit of the device. keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. to optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, i l , is not greater than 30% of the rated output current. figure 26 illustrates the switch and inductor ripple current waveforms. once the input voltage, output voltage, operating frequency and desired ripple current are known, the minimum value for the inductor can be calculated by the formula shown below: (2) copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 13 product folder links: LM20333 l min = (v in - v out ) x d ' i l x f sw c in1 vin sw agnd fb pgood v out r fb1 r fb2 c out en ss/trk vcc c vcc c c1 sync r c1 v in LM20333 boot gnd l c boot d1 (optional) c ss r pg v pullup c in2 comp d = v out v in
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com figure 26. switch and inductor current waveforms if needed, slightly smaller value inductors can be used, however, the peak inductor current, i out + i l /2, should be kept below the peak current limit of the device. in general, the inductor ripple current, i l , should be more than 10% of the rated output current to provide adequate current sense information for the current mode control loop. if the ripple current in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability. output capacitor selection (c out ) the output capacitor, c out , filters the inductor ripple current and provides a source of charge for transient load conditions. a wide range of output capacitors may be used with the LM20333 that provide excellent performance. the best performance is typically obtained using ceramic, sp or oscon type chemistries. typical trade-offs are that the ceramic capacitor provides extremely low esr to reduce the output ripple voltage and noise spikes, while the sp and oscon capacitors provide a large bulk capacitance in a small volume for transient loading conditions. when selecting the value for the output capacitor, the two performance characteristics to consider are the output voltage ripple and transient response. the output voltage ripple can be approximated by using the following formula: where ? v out (v) is the amount of peak to peak voltage ripple at the power supply output ? r esr ( ? ) is the series resistance of the output capacitor ? f sw (hz) is the switching frequency ? c out (f) is the output capacitance used in the design (3) the amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. keep in mind ceramic capacitors are sometimes preferred because they have very low esr; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. the output capacitor selection will also affect the output voltage droop during a load transient. the peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation: 14 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333 ' v out = ' i l x 1 8 x f sw x c out r esr + v in i l avg = i out ' i l time time i l v sw
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 where ? c out (f) is the minimum required output capacitance ? l (h) is the value of the inductor ? v droop (v) is the output voltage drop ignoring loop bandwidth considerations ? i outstep (a) is the load step change ? r esr ( ? ) is the output capacitor esr ? v in (v) is the input voltage ? v out (v) is the set regulator output voltage (4) both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple or transient droop target. input capacitor selection good quality input capacitors are necessary to limit the ripple voltage at the vin pin while supplying most of the switch current during the on-time. in general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. one important note is to use a good dielectric for the ceramic capacitor such as x5r or x7r. these provide better over temperature performance and also minimize the dc voltage derating that occurs on y5v capacitors. the input capacitors c in1 and c in2 should be placed as close as possible to the vin and gnd pins on both sides of the device. non-ceramic input capacitors should be selected for rms current rating and minimum ripple voltage. a good approximation for the required ripple current rating is given by the relationship: (5) as indicated by the rms ripple current equation, highest requirement for rms current rating occurs at 50% duty cycle. for this case, the rms ripple current rating of the input capacitor should be greater than half the output current. for best performance, low esr ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. setting the output voltage (r fb1 , r fb2 ) the resistors r fb1 and r fb2 are selected to set the output voltage for the device. table 1 provides suggestions for r fb1 and r fb2 for common output voltages. table 1. suggested values for r fb1 and r fb2 r fb1 (k ? ) r fb2 (k ? ) v out short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 52.3 10 5.0 if different output voltages are required, r fb2 should be selected to be between 4.99 k ? to 49.9 k ? and r fb1 can be calculated using the equation below. (6) copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 15 product folder links: LM20333 i in-rms = i out d(1 - d) v droop = ' i outstep x r esr + l x ' i outstep 2 c out x (v in - v out ) r fb1 = - 1 v out 0.8 x r fb2
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com loop compensation (r c1 , c c1 ) the purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. optimal loop compensation depends on the output capacitor, inductor, load and the device itself. table 2 below gives values for the compensation network that will result in a stable system when using a 150 f, 6.3v poscap output capacitor (6tpb150mazb). table 2. recommended compensation for c out = 150 f, i out = 3a, f sw = 500khz v in v out l ( h) r c (k ? ) c c1 (nf) 12 5 6.8 30.9 4.7 12 3.3 5.6 33.2 3.3 12 2.5 4.7 40.2 2.2 12 1.5 3.3 22.1 2.2 12 1.2 2.2 18.2 2.2 12 0.8 1.5 8.45 3.3 5 3.3 2.2 38.3 2.2 5 2.5 3.3 38.3 2.2 5 1.5 2.2 30.1 2.2 5 1.2 2 18.2 2.2 5 0.8 1.5 13 2.2 if the desired solution differs from the table above the loop transfer function should be analyzed to optimize the loop compensation. the overall loop transfer function is the product of the power stage and the feedback network transfer functions. for stability purposes, the objective is to have a loop gain slope that is -20db/decade from a very low frequency to beyond the crossover frequency. figure 27 shows the transfer functions for power stage, feedback/compensation network, and the resulting compensated loop for the LM20333. figure 27. LM20333 loop compensation the power stage transfer function is dictated by the modulator, output lc filter, and load; while the feedback transfer function is set by the feedback resistor ratio, error amp gain and external compensation network. 16 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333 a m f sw /2 0 db frequency (hz) gain (db) error amp zero, f z(ea) complex double pole, f p(mod) optional error amp pole, f p2(ea) 0 db 0 db a ea + a m error amplifier transfer function modulator and output filter transfer function compensated open loop transfer function a ea error amp pole, f p1(ea) complex double pole, f p(mod) output filter zero, f z(fil) output filter pole, f p(fil) f c error amp pole, f p(ea)
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 to achieve a -20db/decade slope, the error amplifier zero, located at f z(ea) , should be positioned to cancel the output filter pole (f p(fil) ). compensation of the LM20333 is achieved by adding an rc network as shown in figure 28 below. figure 28. compensation network for LM20333 a good starting value for c c1 for most applications is 2.2 nf. once the value of c c1 is chosen the value of rc should be approximated using the equation below to cancel the output filter pole (f p(fil) ) as shown in figure 27 . (7) a higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of c c1 and recalculating the value of r c1 . likewise, increasing c c1 and recalculating r c1 will provide additional phase margin at a lower crossover frequency. as with any attempt to compensate the LM20333 the stability of the system should be verified for desired transient droop and settling time. for low duty cycle operation, when the on time of the switch node is less than 200ns, an additional capacitor (c c2 ) should be added from the comp pin to agnd. the recommended value of this capacitor is 20pf. if low duty cycle jitter on the switch node is observed, the value of this capacitor can be increased to improve noise immunity; however, values much larger than 100pf will cause the pole f p2(ea) to move to a lower frequency degrading loop stability. boot capacitor (c boot ) the LM20333 integrates an n-channel buck switch and associated floating high voltage level shift / gate driver. this gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. a 0.1 f ceramic capacitor, connected with short traces between the boot pin and sw pin, is recommended. during the off-time of the buck switch, the sw pin voltage is approximately 0v and the bootstrap capacitor is charged from vcc through the internal bootstrap diode. sub-regulator bypass capacitor (c vcc ) the capacitor at the vcc pin provides noise filtering for the internal sub-regulator. the recommended value of c vcc should be no smaller than 0.1 f and no greater than 1 f. the capacitor should be a good quality ceramic x5r or x7r capacitor. in general, a 1 f ceramic capacitor is recommended for most applications. the vcc regulator should not be used for other functions since it isn't protected against short circuit. setting the start up time (c ss ) the addition of a capacitor connected from the ss pin to ground sets the time at which the output voltage will reach the final regulated value. larger values for c ss will result in longer start up times. table 3 , shown below provides a list of soft start capacitors and the corresponding typical start up times. table 3. start up times for different soft-start capacitors start up time (ms) c ss (nf) 1 none 5 33 10 68 15 100 20 120 copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 17 product folder links: LM20333 r c1 = x c c1 c out i out v out + -1 2 x d f sw x l comp c c1 r c1 c c2 LM20333 (optional)
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com if different start up times are needed the equation shown below can be used to calculate the start up time. (8) as shown above, the start up time is influenced by the value of the soft-start capacitor c ss and the 4.5 a soft- start pin current i ss . while the soft-start capacitor can be sized to meet many start up requirements, there are limitations to its size. the soft-start time can never be faster than 1 ms due to the internal default 1 ms start up time. when the device is enabled there is an approximate time interval of 50 s when the soft-start capacitor will be discharged just prior to the soft-start ramp. if the enable pin is rapidly pulsed or the soft-start capacitor is large there may not be enough time for c ss to completely discharge resulting in start up times less than predicted. to aid in discharging of soft-start capacitor during long disable periods an external 1m ? resistor from ss/trk to ground can be used without greatly affecting the start up time. using precision enable and power good the precision enable (en) and power good (pgood) pins of the LM20333 can be used to address many sequencing requirements. the turn-on of the LM20333 can be controlled with the precision enable pin by using two external resistors as shown in figure 29 . figure 29. sequencing LM20333 with precision enable the value for resistor r b can be selected by the user to control the current through the divider. typically this resistor will be selected to be between 10 k ? and 49.9 k ? . once the value for r b is chosen the resistor r a can be solved using the equation below to set the desired turn-on voltage. (9) when designing for a specific turn-on threshold (v to ) the tolerance on the input supply, enable threshold (v ih_en ), and external resistors need to be considered to ensure proper turn-on of the device. the LM20333 features an open drain power good (pgood) pin to sequence external supplies or loads and to provide fault detection. this pin requires an external resistor (r pg ) to pull pgood high when the output is within the pgood tolerance window. typical values for this resistor range from 10 k ? to 100 k ? . tracking an external supply by using a properly chosen resistor divider network connected to the ss/trk pin, as shown in figure 30 , the output of the LM20333 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up. figure 30. tracking an external supply 18 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333 ss/trk v out1 r1 r2 en LM20333 external power supply v out2 r a = - 1 v to v ih_en x r b en v out1 r a r b LM20333 external power supply v out2 t ss = 0.8v x c ss i ss
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 since the soft-start charging current i ss is always present on the ss/trk pin, the size of r2 should be less than 10 k ? to minimize the errors in the tracking output. once a value for r2 is selected the value for r1 can be calculated using appropriate equation in figure 31 , to give the desired start up. figure 30 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up. figure 31. common start up sequences a simultaneous start up is preferred when powering most fpgas, dsps, or other microprocessors. in these systems the higher voltage, v out1 , usually powers the i/o, and the lower voltage, v out2 , powers the core. a simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the i/o pins of the processor. the second most common power on behavior is known as a ratiometric start up. this start up is preferred in applications where both supplies need to be at the final value at the same time. similar to the soft-start function, the fastest start up possible is 1ms regardless of the rise time of the tracking voltage. when using the track feature the final voltage seen by the ss/track pin should exceed 1v to provide sufficient overdrive and transient immunity. benefit of an external schottky the LM20333 employs a 40ns dead time between conduction of the control and synchronous fets in order to avoid the situation where both fets simultaneously conduct, causing shoot-through current. during the dead time, the body diode of the synchronous fet acts as a free-wheeling diode and conducts the inductor current. the structure of the high voltage dmos is optimized for high breakdown voltage, but this typically leads to inefficient body diode conduction due to the reverse recovery charge. the loss associated with the reverse recovery of the body diode of the synchronous fet manifests itself as a loss proportional to load current and switching frequency. the additional efficiency loss becomes apparent at higher input voltages and switching frequencies. one simple solution is to use a small 1a external schottky diode between sw and gnd as shown in figure 38 . the external schottky diode effectively conducts all inductor current during the dead time, minimizing the current passing through the synchronous mosfet body diode and eliminating reverse recovery losses. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 19 product folder links: LM20333 v out1 v out2 v en voltage time voltage time simultaneous start up ratiometric start up =1r v out1 v out2 v en out1 2 out vx8.0< v ( ) x -1 =1r 2r v 1 out 2r x -1 v 2 out v8.0 ? 1 ? ?
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com the external schottky conducts currents for a very small portion of the switching cycle, therefore the average current is low. an external schottky rated for 1a will improve efficiency by several percent in some applications. a schottky rated at a higher current will not significantly improve efficiency and may be worse due to the increased reverse capacitance. the forward voltage of the synchronous mosfet body diode is approximately 700 mv, therefore an external schottky with a forward voltage less than or equal to 700 mv should be selected to ensure the majority of the dead time current is carried by the schottky. thermal considerations the thermal characteristics of the LM20333 are specified using the parameter ja , which relates the junction temperature to the ambient temperature. although the value of ja is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. to obtain an estimate of the device junction temperature, one may use the following relationship: t j = p d x ja + t a (10) and p d = p in x (1 - efficiency) - 1.1 x (i out ) 2 x dcr where ? t j is the junction temperature in c ? p in is the input power in watts (p in = v in x i in ) ? ja is the junction to ambient thermal resistance for the LM20333 ? t a is the ambient temperature in c ? i out is the output load current ? dcr is the inductor series resistance (11) it is important to always keep the operating junction temperature (t j ) below 125 c for reliable operation. if the junction temperature exceeds 170 c the device will cycle in and out of thermal shutdown. if thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. figure 32 , figure 33 , figure 34 and figure 35 can be used as a guide to avoid exceeding the maximum junction temperature of 125 c provided an external 1a schottky diode, such as central semiconductor's cmmsh1-40- nst, is used to improve reverse recovery losses. figure 32. safe thermal operating areas (i out = 3a, f sw = 350khz) 20 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 figure 33. safe thermal operating areas (i out = 3a, f sw = 500khz) figure 34. safe thermal operating areas (i out = 3a, f sw = 750khz) figure 35. safe thermal operating areas (i out = 2.5a, f sw = 500khz) the dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature. this data for the figure was derived assuming the device is operating at 3a continuous output current on a 4 layer pcb with a copper area greater than 4 square inches exhibiting a thermal characteristic less than 27 c/w. since the internal losses are dominated by the fets a slight reduction in current by 500ma allows for much larger regions of operation, as shown in figure 35 . copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 21 product folder links: LM20333
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com figure 36 , shown below, provides a better approximation of the ja for a given pcb copper area. the pcb used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. to provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias located under the thermal pad was used to connect the 4 layers. figure 36. thermal resistance vs pcb area (4 layer board) pcb layout considerations pc board layout is an important part of dc-dc converter design. poor board layout can disrupt the performance of a dc-dc converter and surrounding circuitry by contributing to emi, ground bounce, and resistive voltage loss in the traces. these can send erroneous signals to the dc-dc converter resulting in poor regulation or instability. good layout can be implemented by following a few simple design rules. 1. minimize area of switched current loops. in a buck regulator there are two loops where currents are switched at high slew rates. the first loop starts from the input capacitor, to the regulator vin pin, to the regulator sw pin, to the inductor then out to the output capacitor and load. the second loop starts from the output capacitor ground, to the regulator gnd pins, to the inductor and then out to the load (see figure 37 ). to minimize both loop areas the input capacitor should be placed as close as possible to the vin pin. grounding for both the input and output capacitor should consist of a small localized top side plane that connects to gnd and the exposed pad (ep). the inductor should be placed as close as possible to the sw pin and output capacitor. 2. minimize the copper area of the switch node. since the LM20333 has the sw pins on opposite sides of the package it is recommended that the sw pins should be connected with a trace that runs around the package. the inductor should be placed at an equal distance from the sw pins using 100 mil wide traces to minimize capacitive and conductive losses. 3. have a single point ground for all device grounds located under the ep. the ground connections for the compensation, feedback, and soft-start components should be connected together then routed to the ep pin of the device. the agnd pin should connect to gnd under the ep. if not properly handled poor grounding can result in degraded load regulation or erratic switching behavior. 4. minimize trace length to the fb pin. since the feedback node can be high impedance the trace from the output resistor divider to fb pin should be as short as possible. this is most important when high value resistors are used to set the output voltage. the feedback trace should be routed away from the sw pin and inductor to avoid contaminating the feedback signal with switch noise. 5. make input and output bus connections as wide as possible. this reduces any voltage drops on the input or output of the converter and can improve efficiency. voltage accuracy at the load is important so make sure feedback voltage sense is made at the load. doing so will correct for voltage drops at the load and provide the best output accuracy. 6. provide adequate device heatsinking. for most 3a designs a four layer board is recommended. use as many vias as is possible to connect the ep to the power plane heatsink. for best results use a 5x4 via array with a minimum via diameter of 12 mils. "via tenting" with the solder mask may be necessary to prevent wicking of the solder paste applied to the ep. see the thermal considerations section to ensure enough copper heatsinking area is used to keep the junction temperature below 125 c. 22 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
LM20333 www.ti.com snvs558c ? may 2008 ? revised january 2009 figure 37. schematic of LM20333 highlighting layout sensitive nodes figure 38. typical application schematic copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 23 product folder links: LM20333 pvin sw pgnd l v out LM20333 c in c out loop1 loop2 v in v out c1 c9 r4 r3 r1 c8 c2 c4 d1 r2 c5 c3 LM20333 fb agnd sw gnd gnd gnd u1 14 11 12 2 10 9 sw 13 sw 8 sw 7 boot 17 vin 16 vin 15 vin 6 vin 5 ep comp 4 ss 1 sync 20 pgood 3 en 19 vcc 18 c7 l1 c6 v out pgood enable sync gnd gnd c2, c3 should be placed at vin pins 5,6 and 15,16 respectively. (optional for improved efficiency)
LM20333 snvs558c ? may 2008 ? revised january 2009 www.ti.com table 4. bill of materials (v in = 12v, v out = 3.3v, i out = 3a, f sw = 500khz) id qty part number size description vendor u1 1 LM20333mh htssop ic, switching regulator ti c1 1 c3225x5r1e226m 1210 22 f, x5r, 25v, 20% tdk c2, c3 2 grm21br61e475ka12l 0805 4.7 f, x5r, 25v, 10% murata c5, c6 1 c1608x7r1h104k 0603 100nf, x7r, 50v, 10% tdk c4 1 c1608x5r1a105k 0603 1 f, x7r, 10v, 10% tdk c7 1 c1608c0g1h100j 0603 10pf, c0g, 50v, 5% tdk c8 1 c1608c0g1h152j 0603 1.5nf, c0g, 50v, 5% tdk c9 1 6tpb150mazb b 150 f,poscap, 6.3v, 20% sanyo d1 1 cmmsh1-40-nst sod123 vr = 40v, io = 1a, vf = 0.55v central semiconductor l1 1 ihlp4040dzer5r6m01 ihlp4040 5.6 h, 0.018 ohms, 16a vishay r1, r4 2 crcw06031002f 0603 10k ? , 1% vishay r2 1 crcw06031502f 0603 15k ? , 1% vishay r3 1 crcw06033092f 0603 30.9k ? , 1% vishay 24 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder links: LM20333
package option addendum www.ti.com 24-jan-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples LM20333mh/nopb active htssop pwp 20 73 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 20333mh LM20333mhe/nopb active htssop pwp 20 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 20333mh LM20333mhx/nopb active htssop pwp 20 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 20333mh (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) only one of markings shown within the brackets will appear on the physical device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LM20333mhe/nopb htssop pwp 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 LM20333mhx/nopb htssop pwp 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 package materials information www.ti.com 17-nov-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LM20333mhe/nopb htssop pwp 20 250 203.0 190.0 41.0 LM20333mhx/nopb htssop pwp 20 2500 349.0 337.0 45.0 package materials information www.ti.com 17-nov-2012 pack materials-page 2
mechanical da t a pwp0020a www .ti.com m x a 2 0 a ( r e v c )
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